Using the Xilinx Unisim and XilinxCoreLib with GHDL (on Mac OSX)

For my project I partly work on my Mac, on which I cannot use the Xilinx ISE, and the only option to simulate VHDL code is to use GHDL. I was looking for a possibility to still use the IP Cores that I generate with the Xilinx Coregen tool, e.g. FIFOs. I found an article which described how the unisim library can be used  with GHDL. I adapted and improved the method described in the article a little bit. So here is what I did:

First you have to have a computer with the Xilinx ISE installed. From there obtain the Unisim and XilinxCoreLib source files from /opt/Xilinx/14.7/ISE_DS/ISE/vhdl/src/

I copied them to my GHDL directory on my Mac under /usr/local/lib/ghdl/src/xilinx. If you use a different directory this has to be changed in the following scripts.

Compiling the libraries is a bit tricky, because there are interdependencies between the files. But luckily Xilinx provides a file (vhdl_analyze_order in the source folders) that gives us the order in which the files have to be compiled.

To compile the files in the right order, I wrote two little scripts. Here is the script for the unisim library:

# adapt this to your needs:

mkdir -p $output_dir

# First analyze the files in the base directory
ghdl -a --work=$library_name --ieee=synopsys --std=$vhdl_standard --workdir=$output_dir -P$output_dir -fexplicit ${src_dir}/*.vhd

# Then analyze the files in the 'primitive/' sub-directory
# Strip lines that do not start with a alphabetic character
f=$(grep --no-filename -R '^[a-zA-Z]' ${src_dir}/primitive/vhdl_analyze_order)

# compile each file
while read line
        ghdl -a --work=$library_name --ieee=synopsys --std=$vhdl_standard --workdir=$output_dir -P$output_dir -fexplicit ${src_dir}/primitive/$line
done <<< "$f"

And here is a similar script for the XilinxCoreLib:

# adapt this to your needs:
mkdir -p $output_dir
#Strip lines that do not start with a alphabetic character
f=$(grep --no-filename -R '^[a-zA-Z]' ${src_dir}/vhdl_analyze_order)
# compile each file
while read line
        ghdl -a --work=$library_name --ieee=synopsys --std=$vhdl_standard --workdir=$output_dir -P$output_dir -fexplicit ${src_dir}/$line
done <<< "$f"

Save this to a file, e.g. build_XilinxCoreLib, make it executable, then the XilinxCoreLib can be analyzed and added to the library with:


Most of the files are analyzed without problems. Only the following files could not be analyzed, and hence will be missing from the library:

  • xbip_dsp48_macro_v2_1 .vhd
  • xbip_dsp48_macro_v2_0.vhd
  • fir_compiler_v5_1_sim_pkg.vhd
  • fir_compiler_v5_0_sim_pkg.vhd

To use the library use the „-P“ option of ghdl to specify the location of the additional libraries. And because Xilinx uses some non IEEE standard libraries you also have to add the „–ieee=synopsys -fexplicit“ options for example:

ghdl -a -P/usr/local/lib/ghdl/v93/unisim/ -P/usr/local/lib/ghdl/v93/xilinxcorelib/ --ieee=synopsys -fexplicit FIFO.vhd
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